This application claims priority under 35 USC §119 to Korean Patent Application No. 10-2008-0008608, filed on Jan. 28, 2008 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to image sensors, and more particularly, to an image sensor transmitting a large amount of data at high speed.
2. Background of the Invention
FIG. 1 shows a block diagram of a conventional image sensor 10. Referring to FIG. 1, the image sensor 10 includes a pixel array 20, a row decoder 23, a column decoder 25, an analog-to-digital converter (ADC) 27, a timing generator 40, and an output unit 50. The pixel array 20 includes a plurality of unit pixels arranged in a matrix of rows and columns. The pixel array 20 outputs analog signals generated from a received image to the ADC 27.
The row decoder 23 is connected to the pixel array 20 for sequentially selecting rows of the pixel array 20 to output signals in a predetermined order. The column decoder 25 is connected to the pixel array 20 for sequentially selecting columns in the pixel array 20 to output signals via the ADC 27 in a predetermined order.
In other words, the analog signals generated by the pixels as selected by the row decoder 23 and the column decoder 25 are output to the ADC 27. The ADC 27 converts such analog signals from the selected pixels of the pixel array 20 into N-bit data (where N is a natural number, for example, N=10) and outputs the N-bit data to a data bus 29 (FIG. 2). For example, the respective analog signal from each selected pixel is converted by the ADC 27 into a respective N-bit data.
The timing generator 40 generates a first clock signal CLK8 from an external clock signal PCLK. The timing generator 40 includes an 8-bit data formatter 41. The 8-bit data formatter 41 divides 10-bit data (i.e., the N-bit data from the ADC 27) into 8-bit units in response to the first clock signal CLK8. The data formatter 41 outputs a single data set of 8 bits to the output unit 50 in response to the first clock signal CLK8.
FIG. 2 shows a more detailed block diagram of the data bus 29, the timing generator 40, and the output unit 50 with a timing diagram for illustrating operation of such components. Referring to FIG. 2, the output unit 50 includes a serializer 51 and an output buffer 53.
The data bus 29 transmits 10-bit parallel data (i.e., N-bit data) output from the ADC 27 to the timing generator 40 via a plurality of transmission lines. The timing generator 40 generates the first clock signal CLK8 from the external clock signal PCLK. For example, the first clock signal CLK8 has a period that is eight times the period of an intermediate clock signal (PCLK*10) having a frequency that is the external clock signal PCLK frequency multiplied by 10. Thus, the first clock signal CLK8 has a frequency that is ⅛ of the frequency of the intermediate clock signal (PCLK*10). Another words, the first clock signal CLK8 has a frequency that is PCLK*(10/8).
The timing generator 40 includes the 8-bit data formatter 41 that divides the 10-bit parallel data into 8-bit units and outputs the 8-bit units in response to the first clock signal CLK8. For example, when the 8-bit data formatter 41 receives the 10-bit data through the data bus 29, the 8-bit data formatter 41 divides the 10-bit data into an 8-bit unit in response to the first clock signal CLK8 and outputs such 8-bit data in parallel to the serializer 51 in response to the first clock signal CLK8.
Also, the 8-bit data formatter 41 latches the remaining 2-bits of the 10-bit parallel data and then outputs another 8-bit parallel data composed of such latched 2-bits of the prior 10-bit parallel data and 6-bits of a subsequent 10-bit parallel data to the serializer 51. The 8-bit data formatter 41 then latches the remaining 4-bits of such subsequent 10-bit parallel data for generating another 8-bit unit.
Since the 8-bit data formatter 41 receives 10-bit parallel data and outputs 8-bit parallel data to the serializer 51 in response to the first clock signal CLK8, the 8-bit data formatter 41 must wait for the subsequent 10-bit parallel data for outputting all of the 10-bits of any 10-bit parallel data to the serializer 51. Such wait results in undesired delay during data transmission.